The present invention relates to a memory circuit able to temporarily store a first block of data comprising no more than N components, and able to produce a second block of N lines of a component of said data, said memory circuit comprising data banks able to receive data words, and address controllers associated to the data banks.
The invention notably finds its application in digital devices intended for rendering video objects such as, for example, MPEG-4 video decoders, 3D graphics accelerators, video games, digital personal assistants or also mobile telephones.
Such a memory circuit is known in the field of digital image processing, notably for pixel interpolation operations using bidimensional filters. For example, in the case of bidimensional filters of 4xc3x974 pixels, the memory circuit has an organization that is described in FIG. 1. Said memory circuit comprises data banks numbered 0 to 7 in the example chosen. The database contains at least a word of 32 bits (S) comprising the values of a component (C) of 4 horizontally contiguous pixels (p1-p4). In the case of MPEG-4 digital video data the component is luminance Y, chrominance U or V or transparency A. For permitting parallel access to the component block of 4xc3x974 pixels, it is not necessary to place 4 words of 32 vertically contiguous bits in the same database. In consequence, 2 words of 32 vertically contiguous bits are placed in 2 consecutive data banks numbered n modulo-8 and n+1 modulo-8, where modulo-8 is the operation of which the result is the remainder of division by 8. Moreover, the block of the component of 4xc3x974 pixels one wishes to have reading access to may be spanning 2 words of 32 horizontally contiguous bits. In order to permit parallel access to the block of the component of 4xc3x974 pixels, 2 words of 32 horizontally contiguous bits thus must not be placed in the same database. In consequence, 2 words of 32 horizontally contiguous bits are placed in 2 different data banks numbered n modulo-8 and n+4 modulo-8. Thus, such a memory circuit permits parallel reading access to an arbitrary block of 4xc3x974 pixels of a data component such as, for example, the block represented in gray (BLO), without a conflict between the various data banks.
The principle of such a memory circuit is described in the document entitled xe2x80x9cArchitecture d""un accxc3xa9lxc3xa9rateur matxc3xa9riel pour la composition d""objets vidxc3xa9o MPEG-44xe2x80x9dC. Miro, Thxc3xa8se de doctorat à l""Ecole Nationale Supxc3xa9rieure de Txc3xa9lxc3xa9communications, spxc3xa9cialitxc3xa9 xc3xa9lectronique et communications, Feb, 18, 2000.
However, this organization of the internal memory of the memory circuit is devised for a two-dimensional access, that is to say, only for a parallel reading or writing access to one of the components of a pixel block. The organization is optimal when the components which are written in the internal memory come from an external memory where they are stored separately, that is to say, if the words successively written in the internal memory correspond to the same component C of various consecutive pixels p1 to pn (C[p1]-C[pn]). The data supplied by the external memory are often available in coplanar format, that is to say, in the form of a structure successively comprising the various components A, Y, U and V for each pixel pi (A[pi]Y[pi]U[pi]V[pi]). In order to permit three-dimensional access to the data as illustrated in FIG. 2, that is to say, either a parallel reading access (R) through an output circuit (OUT) to a first pixel block of one of the components of said pixels, or a parallel writing access (W) through an external memory (EXT) to a second data block comprising, in succession, the components of each data, these two types of access being independent, a multiplication of the data banks in accordance with the diagram of FIG. 3 is necessary. One thus finds oneself with 32 data banks numbered from 0 to 31 in accordance with the principle explained above. This solution has the disadvantage of being particularly complex to use because it augments the number of data banks and, in consequence, the number of address controllers which make it possible to manage the internal memory.
It is an object of the present invention to propose a memory circuit able to manage in a more simple and efficient way a three-dimensional access of data comprising various components.
For this purpose, the memory circuit according to the present invention is characterized in that the address controllers associated to the data banks are able to store:
N first words of a first component which are mutually vertically contiguous in N first data banks having N different numbers,
N second words of the first component which are mutually vertically contiguous and horizontally contiguous to the N first words, in N second data banks which have N other different numbers, and
N words of a second component, which are mutually vertically contiguous and correspond to the same data as N words of the first component, in data banks which have numbers corresponding to a circular permutation of the database numbers associated to the N words of the first component.
The present invention also relates to a video data decoder comprising an external memory able to produce a first block of video data, the memory circuit described above being able to temporarily store the first video data block and able to produce a second block of n lines of a component of said video data, and a processing device able to process the second video data block.
Such a memory circuit utilizes no more than 2N different data banks if the width of the second data block is such that the latter cannot span more than 2 data words, that is 8 data banks instead of 32 data banks of the solution which would become evident to a person of ordinary skill in the art from the prior art. In fact, the same database is used here for storing various different data components which considerably reduces the number of data banks compared to the state of the art. Thus, the organization of the memory circuit which permits the storage of the data is such that the reading of a data block makes it necessary to read only a single memory address per database to obtain the values in said data block for an arbitrary data component.
The implementation of such a circuit will be facilitated as the number of address controllers has been divided by the number of components. The reduction of the number of data banks thus simplifies the decoding of the addresses and thus the overall size of the memory. In consequence, thanks to these instances of parallel access, it is possible to read or write rapidly in the memory circuit at relative low cost.